Power consumption poses a serious problem in modern computer systems. This is especially true in mobile systems, which are typically powered by batteries. The more power the system consumes, the less time the system can operate using a given size battery. In order to extend the operation time, while meeting the increased power demand, additional batteries may be added. Additional batteries are bulky and heavy however. Given the trend towards producing smaller and lighter mobile systems, this solution is not desirable. Alternatively, there are exotic batteries available that provide an increase in operation time without increasing the weight of the system. These batteries can, however, be quite expensive and reduction of system cost is also an important goal. Therefore, neither of these solutions is satisfactory.
The greatest amount of power consumption within a CMOS chip occurs on the leading and trailing edges of clock pulses (i.e., when a clock signal transitions from a low voltage state to a high voltage state, or vice versa). Therefore, when the operating speed of the microprocessor is increased, the number of clock pulses in a particular time period also increases, thereby increasing the power consumption of the microprocessor during this time period. Similarly, a decrease in the operating speed of the microprocessor results in a decrease in the number of clock pulses in a particular time period, thereby decreasing the power consumption of the microprocessor during this time period.
To reduce the power consumption of the system or microprocessor, many different techniques of controlling the clock are used. Typically, the clock continues to toggle during idle time, thereby needlessly consuming power. One method to reduce power by controlling the clock signal is through the use of a dynamic power management system that turns off the clock signal to components while they are idle. This method typically consists of enabling the system or processor component clocks only when the component is needed and disabling the component clocks when the components are not needed. Such a method reduces the overall power consumption of the system or microprocessor by reducing power consumed by idle components.
An alternative method, which can be used independently or in conjunction with the above method of enabling or disabling different components, is to reduce the operating frequency of the clock signal. This method is referred to as frequency reduction. Although it is not always desirable for the system or processor to run at a reduced speed, it can be a useful method of reducing power during times in which it is not necessary for the processor to run at full speed. Frequency reduction is usually accomplished by dividing the clocking signal supplied to the components.
Although this method of dividing the clock is useful in reducing the power consumption of the system, such a method results in the complication of system and component design. For example, in a system in which the microprocessor creates its internal clocks based on a system clock, the system design is complicated when the microprocessor uses a divided clock for power savings. In such a system, depending upon the divide value selected, the falling edges of a divided clock may actually correspond to the rising edge of a non-divided clock. For example, as shown in FIG. 1, in a conventional divide-by-four mode, the falling edge of the divided clock occurs during a rising edge of the non-divided clock. Due to this problem, the external clock (to the microprocessor), which the internal clocks are created from, cannot be used to track the internal clock signals unless additional signals are brought off the microprocessor. The fact that the asserting edges of divided clocks and non-divided clocks do not align also results in a complication of component interface design.
In addition, the above divide method results in the complication of device testing of the component during the divided clock power saving mode. For example, in a dual phase design it is common to combine two phases into a single tester cycle to increase the maximum testing speed. Device timing specifications are normally referenced to occur relative to a specific phase. When the occurrences of the phases are not at a consistent position (as when the deasserting edges of some divided clock align with asserting edges of non-divided clocks) testing becomes more complicated.
Furthermore, in large divide modes, such as divide by 8, 10, 16, etc., there is a long latency associated with waking up from divide mode. In order to prevent glitches on the clock signal, which may adversely affect data integrity, a clock divide must be completed before coming out of divide mode. Therefore, although the system components or processor components may be ready to wake up from the slower operating mode, the clock signal cannot return to its normal operating frequency until it has completed a divide cycle. Therefore, if the components are ready to wake up while in divide by 16, but the clock divide circuitry has just begun the divide count, the component must remain in the slower frequency mode until the divide count reaches 16, or until the divide cycle is complete.